1. Field of the invention
This invention relates to the field of metal-oxide-semiconductor (MOS) memory devices having floating gates and more specifically, to margining of erasable programmable read-only memories (EPROMs).
2. Prior art
The most commonly used EPROM cell has an electrically floating gate which is completely surrounded by insulation and generally disposed between a source and drain regions formed in a silicon substrate. The formation of various EPROM cells are well-known in the prior art. Avalanche injection was used in the earlier EPROM devices, while later versions of EPROMs used channel injection for charging the floating gate. Examples of EPROMs are described in U.S. Pat. Nos. 3,660,819; 4,142,926; 4,114,255; and 4,412,310.
EPROM memories are most often removed from their printed circuit boards for both erasing and programming. A special programming device is used for programming the cells after the cells have been erased. During programming, electrons are transferred to the floating gate making the cells less conductive.
Another floating gate memory is an electrically erasable programmable read-only memory (EEPROM), EEPROMs are typically programmed and erased while installed in the same circuit, such as a printed circuit board, used for reading data from the memory. Examples of EEPROMs are described in U.S. Pat. Nos. 4,203,158; 4,099,196; and 4,460,982.
Electrically erasing some floating gate devices gives rise to a serious problem, specifically undererasing and overerasing. During an erasing sequence some of the cells may not be completely erased, leaving those cells still in a programmed state. Conversely, too much charge can be removed, making the device "depletion-like". Cells are typically tested (verified) after being erased to verify that the floating gate is erased properly.
Similarly in an EPROM, processing variations can cause certain bits in the array to not conduct sufficient current to be properly detected as an erased bit or to seriously delay the detection as an erased bit beyond the specified access time for the chip.
In order to test the memory device, the device is placed into what is typically referred to as a margin mode. This margin mode will allow the detection of the low current bits so that this condition can be repaired through redundancy or the part discarded. A special margining circuit, which is usually "on-chip", is used to provide predetermined margining voltages for taking voltage and/or current readings of the erased cell(s). The margining voltage is used as a reference voltage to make a comparison with the voltage of the tested cell to determine if the cell adequately meets the predetermined margin point or level. Typically, this margin voltage is provided for the purpose of determing a margin current which is a ratio (or percentage) of the normal read current. An example of a floating gate margining is described in a U.S. Pat. No. 4,875,188, issued Oct. 17, 1989 entitled Voltage Margining Circuit For Flash Eprom.